The present invention generally relates to address signal generating circuits for memory circuits, and more particularly to an address signal generating circuit which generates an address signal indicating a value which varies by a predetermined value, and supplies the generated address signal to a memory circuit.
When writing data into a predetermined address in a memory circuit and reading out data from a predetermined address in the memory circuit, it is necessary to use an address signal which specifies the predetermined address, as is well known. The value of such an address signal normally varies by one. However, depending on the kind of data which is to be written into or read out from the memory circuit, it becomes necessary to vary the value of the address signal by a predetermined value.
There is a reproducing apparatus which reproduces recorded signals from a recording medium which is recorded with a component coded signal. The component coded signal is a signal in which picture element data of a digital luminance signal and picture element data of two kinds of digital color difference signals, are time-sequentially multiplexed. The digital luminance signal is obtained by subjecting a luminance signal which is related to a still picture, to a digital pulse modulation. The two kinds of digital color difference signals are obtained by subjecting two kinds of color difference signals which are related to the still picture, to a digital pulse modulation. The above described reproducing apparatus is provided with a memory circuit. The component coded signal which corresponds to one frame (or one field), for example, is written into the memory circuit, and the signals making up the component coded signal which is written in the memory circuit, are read out simultaneously in parallel. These signals making up the component coded signal are repeatedly read out in a predetermined sequence. Because a display device for monitoring the signal which is read out from the memory circuit generally scans horizontally from the left to right of the picture and scans vertically from top to bottom of the picture at a predetermined speed, the picture element data which make up the component coded signal which is written in memory circuit are read out from the memory circuit in agreement with this scanning sequence.
However, when converting the number of scanning lines so as to convert the picture element data of a system which employs 625 scanning lines into the picture element data of a system which employs 525 scanning lines, the picture element data in one scanning line of the 525-line system are formed from the picture element data of the 625-line system in two mutually adjacent scanning lines, namely, one scanning line in the picture related to the first field (odd field) and one scanning line in the picture related to the second field (even field). Hence, in order to facilitate such a conversion, it is preferred that the picture element data of the component coded signal are transmitted from top to bottom of the picture (that is, the picture element data of the first field and the picture element data of the second field are alternately transmitted) and from the left to right of the picture.
The component coded signal which is recorded on the recording medium, may be made up of a picture element data group comprising picture element data which are arranged in a sequence from the picture element data which are displayed at the uppermost part of the picture to the picture element data which are displayed at the lowermost part of the picture, and from the picture element data which are displayed at the leftmost part of the picture to the picture element data which are displayed at the rightmost part of the picture, for example. In this case, the picture element data which are arranged in a sequence different from the read-out sequence, are successively supplied to the memory circuit in the reproducing apparatus. Accordingly, in this case, the value of the write-in address in the memory and the value of the read-out address in the memory, vary with different values. For example, if it is assumed that the picture element data which are to be displayed at locations in agreement with the scanning sequence of the display device described before, are successively read out by incrementing the read-out address in the memory circuit by one from "0", the write-in address must be varied by a value which is the total number of picture element data displayed in one scanning line or an integer division of this total number. That is, if 114 picture element data are displayed in one scanning line, the picture element data which is located at the uppermost and leftmost part of the picture and is first supplied to the memory circuit, is written into the address "0". The picture element data which is located in the second scanning line from the uppermost (the first scanning line of the second field) and leftmost part of the picture and is subsequently supplied to the memory circuit, is written into the address "114". The picture element data which is located in the third scanning line from the uppermost (the second scanning line of the first field) and leftmost part of the picture and is subsequently supplied to the memory circuit, is written into the address "228". The write-in address is thereafter incremented by 114 in this manner. When all of the picture element data located at the leftmost part of the picture have been written into the memory circuit, the picture element data located at the uppermost part which is second from the leftmost part of the picture, is supplied to the memory circuit, and the picture element data from the uppermost to the lowermost part of the picture are thereafter similarly supplied to the memory circuit. Thus, the write-in address is successively incremented by 114 from the address "1".
In the above case, the read-out address must be incremented by one from "0" if the write-in address is incremented by one from "0". When the sequence with which the data are supplied to the memory circuit differs from the read-out sequence, it is necessary to vary the write-in address or the read-out address by a predetermined value.